The integrated circuit industry is driven by Moore's law for scaling to maintain continuous improvement in technological performance and economical sustainability. This defines an integration and densification roadmap in terms of the smallest printable feature or device size. Currently, the densification of integrated circuits is reaching its limits for planar scaling at 22 nm technology node, which leads designers to consider 3-D integration schemes. A manufacturing process based on 3-D integration requires effective metrology or quality control of the fabricated patterns. Scatterometry or Optical Critical Dimension (OCD) is being increasingly adopted as the metrology of choice for 3-D integration due to its non-destructive and penetrative nature along with its high throughput meeting the metrology requirements for 3-D integration based micro-fabrication processes. This is in contrast to the conventionally and widely-adopted metrology based on Scanning Electron Microscopes (CDSEM) which offers only 2-D or top-down imaging and considered in many cases destructive to measured samples.
Among the most important fabrication parameters to control that is detrimental to device performance is the transistor gate line width, the variability of which is subject to tight dimensional specifications set commonly by the International Technology Roadmap for Semiconductor manufacturing (ITRS). Commonly referred to as Line Edge Roughness (LER) or Line Width Roughness (LWR), depending on the spatial frequency of the variability, the term was developed traditionally from the top-down imaging legacy from the CDSEM technology over the past various micro-fabrication technology nodes. However, this variability in general is associated with the surface of the pattern and is largely isotropic. As such, LER and LWR can be generalized to Surface Roughness (SR), given a metrology that is vertical-horizontal bias free, and in this case OCD is.
SR in general can be controlled and reduced for better device performance, but needs to be accurately measured to provide control tools for micro-fabrication process engineers. A key aspect of LER and LWR is that they exhibit random variability. Scatterometry, while ideal for 3-D pattern metrology, is fundamentally incapable of measuring pattern roughness primarily because of their randomness. The reason for this serious shortcoming in measuring random features is that in development and manufacturing environments, only high throughput algorithms can be used for scatterometry modeling.
The most adopted algorithm which meets this requirement is called Rigorous Coupled Wave Analysis (RCWA) which relies on drawing the physical shape of the nano-device pattern in a unit cell then replicating this cell to simulate the entire scatterometry target, or sample. The shape of the device to be dimensionally measured by scatterometry is drawn in the cell very accurately and the optical properties of the various materials constituting the device shape are also included, this often involved effort is usually referred to as OCD modeling or scatterometry model development. Scatterometry utilizes arrayed targets to maximize the diffraction signal resulting from a focused light beam impinging on these targets located usually in the wafer scribe lines or kerfs between chips. As such, any feature drawn in the fundamental cell is exactly copied over the entire simulated target, and since random features are sample-wide there is no way to generate this extended randomness over the entire sample from the fundamental cell alone. To exacerbate this conundrum, it is important to note two points; first, LER in the advanced technology nodes at 14 nm and below may potentially consume up to 40% of the line width Critical Dimension (CD), as LER does not scale down with line width and the ratio of LER/CD continues to increase with shrinking technology nodes. Second, LER cannot be ignored in the scatterometry model since this will lead to significant inaccuracy in the model and fail to deliver the needed metrology value. In order for scatterometry to continue to be adopted as the metrology of choice for 3-D integration, a solution to LER modeling and measurement is required.